WLPoP TM      Wafer-Level Chip-Scale Package-on-Package.

WL-PoP TM "Wafer-Level Chip-Scale Package-on-Package" technology opens up the possibility of nesting / stacking multiple WLCSP's in a single chip-scale outline.

The technology has been developed to uniquely facilitate the near-term, cost-effective stacking of existing chips at the chip-scale without the protracted timeline / risk and high investment levels needed for methods such as Thru-Silicon-Vias (TSV), Thru-Mold-Via (TMV) or embedded die.

Target markets and applications include:

• Heterogeneous / multi-node chip integration

• System-in-Package / Modules

• Combines Flip-chip, "Fan-in" and "Fan-out" Chip-scale packaging.

• Wireless Connectivity "Wearables" IoT

• MEMS Integration

• Power Semiconductors